IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUE J4R Journal Vol. 2 Issue. 1

IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUE

The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].

             In this paper we review the historical developments in this field, both in circuit realizations and in methods of handling multiplevalued design circuit. In the recent years MVL gaining the importance due to its inherent benefits like high speed , low area , and low power(Vm),we found during analysis of MVL, it has great high message communication ability .in earlier work quaternary [mvl0-3] arithmetic operations like addition, subtraction and multiplications presented which use q-b conversion, b-q conversion for implement the arithmetic operation. We proposed half adder and full adder in quaternary to quaternary without any conversion which then lead more optimization at farther level. 

I am very much thankfull to Mr. Vasundara Patel K.S., K.S. Gurumurthy, for giving there valuable guidance towards therwonderful paper , i am also thankful to B. Radanovic, M. Syrzycki, Ricardo Cunha for giving the impotance of MVL techniques This Article is Researched By Prof Abhijit kalbande From PRMCEAM , Badnera and Published by J4R Journal

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